Selecting SerDes IP: start with the channel

A rate is not a complete interface definition

OIF publishes Common Electrical I/O implementation agreements with separate electrical-interface clauses. CEI-05.3 is an authoritative reference for identifying the applicable interface, not a universal specification for every SerDes marketed at a similar rate. Confirm the exact agreement and clause relevant to your design.

Begin with a block diagram: transmitter package, traces, vias, connectors or cable, and receiver package. Name the protocol, modulation, per-lane rate and reach class. Short-reach or long-reach labels should lead to an exact electrical specification, not substitute for one.

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Use the same channel model for every candidate

Specify frequency range, reference planes, de-embedding assumptions and package inclusion. Compare return loss and crosstalk as well as insertion loss. Require the receiver equalization settings and adaptation assumptions used for each result. A nominal simulation is only one row in the evaluation.

Include voltage, temperature, manufacturing variation and aggressor activity. Any quoted eye opening or error rate needs its measurement point, pattern, test duration and processing assumptions. Otherwise, two attractive numbers may describe different experiments.

Separate raw and corrected error performance

Record whether a result is before or after FEC, whether it counts bits or codewords, and which coding configuration applies. A PHY measurement and a packet-loss requirement are different acceptance objects. Assign ownership for the intervening coding, monitoring and recovery functions.

Illustrative statistical check: with independent, stationary bit errors, zero errors in N bits gives an approximate one-sided 95% upper BER bound of 3/N. A bound near 10⁻¹² needs about 3 × 10¹² observed bits, or 30 seconds at 100 Gb/s. This follows from −ln(0.05) ≈ 3, not from an OIF compliance requirement. Burst errors and changing conditions can invalidate the assumptions; use the applicable standard’s test method.

Tie silicon evidence to the quoted macro

Ask for foundry process option, macro version, lane configuration and test-chip context. Document clock requirements, PLL sharing, calibration firmware and test access. Compare power with the same rate, channel and enabled functions. Turn evidence gaps into explicit qualification tasks with owners, rather than treating “silicon proven” as an unbounded guarantee.

Bring these to your IP evaluation

• Provide package-inclusive channel models and operating corners.
• Separate raw BER, corrected errors and system failure criteria.
• Match silicon evidence to the macro and process being licensed.