Choosing PCIe IP: turn link speed into a system budget

Specify the generation and operating mode

PCI-SIG describes PCIe 6.0 as a 64 GT/s architecture using PAM4, FLIT-based encoding, FEC and CRC. These mechanisms affect implementation and verification. This article compares specific PCIe 5.0 and 6.0 characteristics; neither is presented as a universal recommendation or the newest available generation.

Specify root-complex or endpoint role, negotiated width, peer devices, reset sequences and software environment. Backward compatibility in a specification does not establish that your intended topology has been validated in the quoted IP configuration.

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Separate line rate from payload throughput

PCIe 5.0 uses 32 GT/s with 128b/130b encoding. For x4, the one-direction ceiling after this encoding is 32 × 4 × 128/130 ÷ 8 ≈ 15.75 GB/s. This excludes transaction and other protocol overhead; it is not application throughput. Do not compare bidirectional aggregate bandwidth with a one-way workload.

An illustrative 12 GB/s sustained payload target requires about 76.2% of that ceiling. Validate it with a reproducible DMA benchmark stating payload size, direction, outstanding requests and host-memory behavior. Measure latency too. Do not reuse the 128/130 calculation for PCIe 6.0 FLIT mode.

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Review controller and PHY separately

For the controller, create a must-have/optional matrix covering interrupts, DMA boundaries, required translation or virtualization features, error handling and drivers. “PCIe compliant” is not a complete feature list. Document support responsibilities when the controller and PHY have different suppliers.

Supply the intended package/channel models and reference-clock arrangement. PCI-SIG’s implementation webinar distinguishes a simple insertion-loss budget from channel compliance. Ask which measured configuration supports each compliance claim and what remains to be tested on your board.

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Include interoperability in acceptance

Agree named host/device combinations, link training and recovery, power-state transitions and fault-injection cases. A generation upgrade should be justified by useful throughput and validated channel behavior, with a clear integration owner for each unresolved risk.

Bring these to your IP evaluation

• State useful GB/s per direction and latency limits.
• Freeze role, lane count, clocking and channel assumptions.
• Request reproducible throughput and interoperability evidence.